The present invention relates to a synchronization circuit and a synchronization method and the technology, for example, which can be effectively utilized for the phase synchronization technology to be applied to a DLL (or PLL) circuit provided in semiconductor integrated circuit device.
An example of the PLL circuit which can continuously change over coarse adjustment and fine adjustment is disclosed in the Japanese Published Unexamined Patent Application No. Hei 08(1996)-307254. Moreover, an example of a frequency multiplying circuit including a combining circuit is disclosed in the Japanese Published Unexamined Patent Application No. 11(1999)-004145.
[Patent Document 1]
Japanese Published Unexamined Patent Application No. Hei 08(1996)-307254
[Patent Document 2]
Japanese Published Unexamined Patent Application No. Hei 11(1999)-004145